1. Field of the Invention
The embodiments of the invention generally relate to testing, and more specifically, to increasing the effectiveness of delay and transition fault testing.
2. Description of the Related Art
Conventional scan based delay and transition fault testing methods combine multiple domains together using the limited number of test clocks entering the design. Therefore these conventional scan based delay and transition fault testing methods have limited resolution and consequently require low test clock skew over disparate domains and/or over large regions of the same domain.
At speed structural testing is a recent advancement in the ability to perform delay testing of integrated circuits. At speed structural testing exploits the functional clocks in the design, and can therefore run testing at the functional speed of the circuit design. This provides an advantage over scan based delay and transition fault testing. However, at speed structural testing does not provide complete test coverage and has a limited ability to cover cross-clock-domain paths. Therefore, conventional scan based delay and transition fault testing can still be required to augment at speed structural testing. In this application the term “domain” is interpreted broadly and comprises, digital logic, memory array, analog, and mixed-signal domains which may combine digital and analog.
Conventional delay and transition fault testing has the ability to identify defects or faults missed by at speed structural testing and similar tests. Moreover, the defects or faults missed by at speed structural testing tend to be in the longer more complicated paths where the delay variation is averaged over many elements. Delay and transition fault testing is most effective on long timing paths, where the inaccuracy is a smaller percentage of the domain's cycle time.
In circuits implemented with Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), custom logic, and microprocessors, the circuits may be functional at slower frequencies. However, timing defects in these circuits may cause the design not to work at the designed operating frequency.
These defects make this broad universe of electronic devices susceptible to failure at high clock frequency where circuit paths tend to have less margin or tolerance. As fabrication and other process improvements further reduce operational cycle times, even smaller defects must be identified to ensure implemented circuits operate properly.
For example, conventional FPGA delay testing places built-in self-test structures at various locations around the chip. Each built-in self-test structure contains a test pattern generator that applies test vectors to paths, and an output response analyzer that detects faults in those paths. Conventional built-in self-test techniques access internal paths unreachable by external test equipment. However, the accuracy of conventional built-in self-test techniques are insufficient for designs with small timing margins. These problems arise with a broad universe of electronic devices.
For example, the techniques described in Chmelar's paper (“FPGA Interconnect Delay Fault Testing,” in Proc. IEEE Int'l Test Conf., Vol. 1, pp. 1239-247, 2003) detected faults as small as 360 pico seconds (ps). However, as operating frequencies continue to increase, there is a need to be capable of detecting even smaller timing defects in FPGA and a broad universe of electronic devices.